Index "Z"Available in space-saving MSOP package Ultra low current shutdown mode BTL output can drive capacitive loads Improved pop & click circuitry eliminates noise during turn-on and turn-off transitions 2.0 - 5.5V operation No output coupling capacitors, snubber networks or bootstrap capacitors required Unity-gain stable External gain configuration capability
Vendor:ZTED/C:N/A
is the analog output voltage for white condition is the analog output voltage for dark condition is the device responsivity for a given wavelength of light given in V/(µJ/cm2) is the incident irradiance in µW/cm2 is integration time in seconds
Package Cooled:MODULED/C:03+
Vendor:ZETEXPackage Cooled:SOP-14D/C:06+
NOTE 1: Standard tolerance on JEDEC types shown is +/- 10%. Suffix letter A denotes +/- 5% tolerance; suffix letter C denotes +/- 2%; and suffix letter D denotes +/- 1% tolerance. NOTE 2: Voltage measurements to be performed 20 seconds after application of dc test current. NOTE 3: Zener impedance derived by superimposing on IZT, a 60 cps, rms ac current equal to 10% IZT (2mA ac). See MicroNote 202 for typ...
Vendor:ZETEXPackage Cooled:TSSOPD/C:06+
NOTE 1: Standard tolerance on JEDEC types shown is +/- 10%. Suffix letter A denotes +/- 5% tolerance; suffix letter C denotes +/- 2%; and suffix letter D denotes +/- 1% tolerance. NOTE 2: Voltage measurements to be performed 20 seconds after application of dc test current. NOTE 3: Zener impedance derived by superimposing on IZT, a 60 cps, rms ac current equal to 10% IZT (2mA ac). See MicroNote 202 for typ...
Vendor:ZETEXPackage Cooled:SOP-16D/C:05+
The PVN013 Series Photovoltaic Relay at 100 milliohms features the lowest possible on-state resistance in a miniature package lower than a comparable reed relay. The PVN013 is a single-pole, normally open solid- state relay. It utilizes a GenerationV HEXFET output switch, driven by an integrated circuit photovoltaic generator of novel construction. The output switch is controlled by radiation from...
Vendor:ZETEXPackage Cooled:SOP-16D/C:06+
The PVN013 Series Photovoltaic Relay at 100 milliohms features the lowest possible on-state resistance in a miniature package lower than a comparable reed relay. The PVN013 is a single-pole, normally open solid- state relay. It utilizes a GenerationV HEXFET output switch, driven by an integrated circuit photovoltaic generator of novel construction. The output switch is controlled by radiation from...
Vendor:in stockPackage Cooled:TID/C:04+
• Fully Compliant to IrDA Data 1.2 Low Power Specifications • Ultra Small Package • Minimal Height: 2.5 mm • 2.7 to 3.6 VCC • Low Shutdown Current C 10 nA Typical • Complete Shutdown C TXD, RXD, PIN Diode • Three External Components • Temperature Performance Guaranteed, C25˚C to +85˚C • 25 mA LED Drive Current • Integ...
Vendor:ZETEXPackage Cooled:SOP16D/C:02+
Electrical Characteristics AVIN = PVIN = 5V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA = TJ = +25˚C. Limits appearing in boldface type apply over full Oper- ating Junction Temperature Range (−40˚C to +125˚C). Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Vendor:ZETEXPackage Cooled:SOP8
The circuit in Figure 4 uses the MAX5160 (a 32-tap digital pot) with two fixed precision resistors to finely tune around a specific output voltage. The tuning resolution is increased and the range is decreased as the ratio of the total fixed resistance to the digital pot resistance is increased. Table 1 shows the resistor-value selection optimized to achieve 0.5% tuning accuracy. These resistor values can b...
The key parameters of a damper diode are the peak forward voltage (VFP), the forward voltage (VF ) and the recovery time (trr). Reverse recovery time : trr The table in fig.1 gives the maximum reverse recovery time for the three high frequency damper diodes.
Hynix HYMD264726A(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 64Mx72 high-speed memory arrays. Hynix HYMD264726A(L)8J-Jseries consists of eighteen 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD264726A(L)8J-J series provide a high performance 8-byte interface in 5.25" width form ...
Hynix HYMD264726A(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 64Mx72 high-speed memory arrays. Hynix HYMD264726A(L)8J-Jseries consists of eighteen 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD264726A(L)8J-J series provide a high performance 8-byte interface in 5.25" width form ...
Vendor:ZETEXPackage Cooled:N/AD/C:02+
The HYM72V12C736B(L)S4 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 1Gbytes memory. The HYM72V12C736B(L)S4 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are inter- nally pipelined to achieve very high bandwidth.
Vendor:SANYOPackage Cooled:DIP-30D/C:02+
180-240V AC input, 50/60 Hz 3-phase rectifier bridge 3-phase, short circuit rated, ultrafast IGBT inverter HEXFRED ultrafast soft recovery freewheeling diodes Low inductance (current sense) shunts in positive and negative DC rail NTC temperature sensor Pin-to-baseplate isolation 2500V rms Easy-to-mount two-screw package Case temperature range -25C to 125C operational
Vendor:ZETEXD/C:07+
5) Next, a heat sink with lower SA than the one calcu- lated in step 4 must be selected. One way to do this is to simply look at the graphs of the "Heat Sink Temp Rise Above the Ambient" vs. the "Power Dissipation" and select a heat sink that results in lower tempera- ture rise than the one calculated in the previous step. The following heat sinks from AAVID and Thermalloy m...
Note 5: Rise and fall times are measured using 10% and 90% levels. Duty cycle and nonoverlap times are measured using 50% levels. Note 6: Guaranteed by design, not subject to test. Note 7: PVCC1 must be higher than VCC by at least 2.5V for TG to operate at 95% maximum duty cycle and for the current limit protection circuit to be active. Note 8: The current limiting amplifier can sink but cannot source curr...
Vendor:ZETEXPackage Cooled:TSOT23-5D/C:06+
The specifications on this data book are only given for information, without any guarantee as regards either mistakes or omissions. The application circuit in this data book are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
Vendor:380
The ICS728 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section shown must be followed.
Vendor:N/APackage Cooled:N/AD/C:08+09+
The MAX4060/MAX4062 are capable of switching their output between the differential input and a single- ended auxiliary microphone amplifier input. In addition, the MAX4060/MAX4062 have a low-noise microphone bias generator. The differential gain of the MAX4061/MAX4062 is set with a single resistor. The MAX4060 has a fixed gain of 10V/V and is PC99/2001 compliant. The MAX4061 includes a complete shut- down m...
Vendor:ZETEXPackage Cooled:TSOT23-5D/C:06+
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored, and the refresh address is generated internally.
Vendor:ZETEXPackage Cooled:TSOT23-5D/C:08+
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored, and the refresh address is generated internally.
Package Cooled:SOT-23D/C:05+
The availability of the bias current terminal, IABC , allows the device to be gated for multiplexer applications. Figure 5 shows a simple two-channel multiplexer system using two CA3080 OTA devices. The maximum level-shift from input to output is low (approximately 2mV for the CA3080A and 5mV for the CA3080). This shift is determined by the amplifier input offset voltage of the particular device used, ...
Vendor:ZETEXPackage Cooled:SOT-23D/C:08+
This block provides the RTC reference values to be pro- cessed on the RTC Data Processor Block. The setting of RTC reference values is provided by the external EEPROM in normal condition. If the external EEPROM is not present it will use the internal ROMs RTC reference values. The RTC reference values are the new gray values depending on the difference between the current frames RGB gray data and the ...
Package Cooled:SOT-23D/C:03+
Initial Release Updated Minimum Voltage Condition on page 5 Updated Analog Dynamic Performance for 3.3 V operation on page 6 Updated Full Scale Output Voltage on page 6 Updated High-Level Input Voltage on page 8 Updated Current Consumption Specifications on page 8 Corrected specifications for Internal SCLK Mode on page 9 Updated VQ in Recommended Connection Diagram on page 11 Updated Ramp Times for Output T...
Vendor:ZETEXPackage Cooled:SOT-23D/C:08+
The function of the Data Output register can be controlled by the user via the FT mode pin/bump (Pin 14 in the TQFP, Bump 1F in the FP-BGA). Holding the FT mode pin/bump low, places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
Package Cooled:ZETEXD/C:07+
IN2 is connected to Pin 16 (VCCA). A ferrite antenna is connected between IN1 and IN2. Q of antenna circuit should be as high as possible, but the temperature influence must be compensated. The resonant resistance should be 200 kW to 300 kW for optimal sensitivity.
Vendor:ZETEXPackage Cooled:SOT-23D/C:08+
The PAL22V10Z contains a programmable design security cell. Programming this cell will disable the read verify and programming circuitry protecting the design from being copied. The security cell is usually programmed after the design is finalized and released to production. A secured device will verify as if every location in the device is programmed. Because programming is accomplished by storing an in...
Package Cooled:SOT-23D/C:05+
The EM128L08 is an integrated memory device containing a low power 1 Mbit Static Random Access Memory organized as 131,072 words by 8 bits. The device is fabricated using NanoAmps advanced CMOS process and high-speed/low- power circuit technology. This device is designed for very low voltage operation making it quite suit- able for battery powered devices.It is also designed for both very low operating and ...
Package Cooled:SOT-23D/C:05+
The EM128L08 is an integrated memory device containing a low power 1 Mbit Static Random Access Memory organized as 131,072 words by 8 bits. The device is fabricated using NanoAmps advanced CMOS process and high-speed/low- power circuit technology. This device is designed for very low voltage operation making it quite suit- able for battery powered devices.It is also designed for both very low operating and ...
Vendor:ZETEXPackage Cooled:SOT-23D/C:08+
Vendor:ZETEXPackage Cooled:SOT-23D/C:08+
Vendor:ZETEXPackage Cooled:ZETEXD/C:2006
Note 1: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Vendor:ZETEXPackage Cooled:SOT23-6D/C:05+
5.0V and 3.3V Versions at 100mA Output Very Low Quiescent Current Low Dropout Voltage: 380mV at 100mA Extremely Tight Load and Line Regulation Very Low Temperature Coefficient Current & Thermal Limiting Need Only 1 µF for Stability Offered in TO-92 (LP2950) & SOIC (LP2951) Direct Replacement For LP2950/LP2951
Vendor:ZETEXPackage Cooled:SOT23-6D/C:05+
This device is a low-cost, high-speed, JFET-input operational amplifier with very low input offset voltage. It requires low supply current yet maintains a large gain-bandwidth product and a fast slew rate. In addition, the matched high-voltage JFET input provides very low input bias and offset currents.
Vendor:ZETEXPackage Cooled:50000D/C:04+
C Selectable auto-mute C Selectable 32, 44.1, and 48 kHz de-emphasis filters C Configurable ATAPI mixing functions C Configurable volume and muting controls C Selectable serial audio interface formats Left justified up to 24-bit I²S up to 24-bit Right justified 16, 18, 20, and 24-bit
Vendor:ZETEXPackage Cooled:SOT-223D/C:04+
C Selectable auto-mute C Selectable 32, 44.1, and 48 kHz de-emphasis filters C Configurable ATAPI mixing functions C Configurable volume and muting controls C Selectable serial audio interface formats Left justified up to 24-bit I²S up to 24-bit Right justified 16, 18, 20, and 24-bit
Vendor:ZETEXPackage Cooled:SOT23-6D/C:06+
Designed utilizing CMOS process technology, the FAN2502/03 family of products are carefully optimized for use in compact battery-powered devices, offering a unique combination of low power consumption, extremely low dropout voltages, high tolerance for a variety of output capacitors, and the ability to disable the output to less than 1µA under user control. In the circuit, a difference ampliʂ...
Vendor:ZETEXPackage Cooled:SOT-163D/C:6
To close the feedback loop of the PI6C2308A, the FBK pin can be driven from any of the 8 available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is shown in the graph above.
Vendor:SOT-163Package Cooled:SOT23-6D/C:12000
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.9 ns at 1.8 V Low Power Consumption, 10-µA Max ICC 8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 C 2000-V Human-Body Model (A114-A) C 200-V Machine Model (A...
Fully programmed sequencing control ramps the back-end plane voltages in order, and during shutdown from a healthy state, turns off the back-end supplies in the reverse order. In addition, electronic circuit breakers provide continuous protection for the system supplies during the plug-in operation. The TTL/CMOS-compatible ENABLE input and the board power good signal (PG) can interface directly to the indi...
Vendor:ZETEXPackage Cooled:MSOP-8D/C:00+
Vendor:ZETEXPackage Cooled:2005D/C:2400
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed b...
Vendor:ZETEXPackage Cooled:2005D/C:04+
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed b...
Vendor:ZETEXPackage Cooled:MSOP-8D/C:00+
When used as a decimating post-filter with a double speed oversampling analog-digital converter, the device greatly reduces the cost and complexity of the associated analog anti-aliasing pre-filter. In a similar fashion, when used as an interpolating pre-filter with a double speed oversampling digital- analog converter, the GF9102A simplifies the analog reconstruction post-filter. The GF9102A also exceeds the...
Vendor:ZETEXD/C:2005
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech- nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?72341.
Vendor:ZETEXPackage Cooled:MSOP-8D/C:00+
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel con- version). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the ENABLE input be high during serial data entry.
Vendor:ZETEXPackage Cooled:MSOP8D/C:05+
Thaler Corporation has developed a nonlinear compensation network of thermistors and resistors that is used in the VRE series voltage references. This proprietary network eliminates most of the nonlinearity in the voltage vs. temperature function. By adjusting the slope, Thaler Corporation produces a very stable voltage over wide temperature ranges.
Vendor:ZETEXD/C:04+
• Four Crystal modes, up to 25 MHz • 4X Phase Lock Loop (PLL) (available for crystal and internal oscillators) • Two External RC modes, up to 4 MHz • Two External Clock modes, up to 40 MHz • Internal oscillator block: - 8 user selectable frequencies, from 31 kHz to 8 MHz - Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL - User tu...
Vendor:ZetexPackage Cooled:SO-8D/C:2006+
• Message bit rates up to 1 Mbps • Conforms to CAN 2.0B ACTIVE Specification • Fully backward compatible with PIC18XXX8 CAN modules • Three modes of operation: - Legacy, Enhanced Legacy, FIFO • Three dedicated transmit buffers with prioritization • Two dedicated receive buffers • Six programmable receive/transmit buffers • Three full 29-bit acceptan...
Vendor:ZetexPackage Cooled:SO-8D/C:2006+
• Message bit rates up to 1 Mbps • Conforms to CAN 2.0B ACTIVE Specification • Fully backward compatible with PIC18XXX8 CAN modules • Three modes of operation: - Legacy, Enhanced Legacy, FIFO • Three dedicated transmit buffers with prioritization • Two dedicated receive buffers • Six programmable receive/transmit buffers • Three full 29-bit acceptan...
Vendor:ZETEXPackage Cooled:MSOP-8D/C:06+
Notes: 1. Worst case values occur at an IC junction temperature of 125C. 2. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied together. 3. Changing the logic levels of the Address lines when CE = "0" may cause erroneous data to be entered into the Character RAM, regardless of the logic levels of the WR an...
Package Cooled:08+D/C:2000
An internal three-line adaptive comb decoder structure pro- duces optimal picture quality with a wide range of source material. NTSC/PAL field and NTSC frame based decoding is supported with external memory. Full comb programma- bility allows the user to tailor the decoders response to a particular systems goals.
D/C:2000
An internal three-line adaptive comb decoder structure pro- duces optimal picture quality with a wide range of source material. NTSC/PAL field and NTSC frame based decoding is supported with external memory. Full comb programma- bility allows the user to tailor the decoders response to a particular systems goals.
Vendor:ZETEXPackage Cooled:07+
s 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. s 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory. 128-bit wide interface/accelerator enables high-speed 60 MHz operation. s In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader software. Single flash sector or full chip erase in 400 ms and programming of 256 by...
Vendor:ZETEXPackage Cooled:MSOP-8D/C:06+
Although TX and RX cores are physically separate, each channel can perform a built-in-self-test (BIST) using a PRBS pattern in a serial loopback mode.The TX LVDS drivers have programmable output levels allowing the user to tune the driver for specific transmission channels.
Vendor:ZETEXD/C:04+
The following are trademarks of Conexant Systems, Inc.: Conexant, the Conexant C symbol, and Whats Next in Communications Technologies. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners.
Vendor:ZETEXPackage Cooled:MSOP-8D/C:05+
The FAN2500/01 is designed to supply 100mA at the specified output voltage with an operating die (junction) temperature of up to 125C. Once the power dissipation and thermal resistance is known, the maximum junction temperature of the device can be calculated. While the power dissipation is calculated from known electrical parameters, the thermal resistance is a result of the thermal characteris-...
Vendor:ZETEXPackage Cooled:MSOP-8D/C:6
The LH1526 relay is two SPST normally open switches that can replace electromechanical relays in many applications. The relays require a minimal amount of LED drive current to operate, making it ideal for battery powered and power consumption sensitive applications. The relay is constructed using a GaAIAs LED for actuation control and an integrated monolithic die for the switch output. The die is, fa...
Vendor:ZETEXD/C:04+
2. Instruction X just changes its data field (in time slot Y). (Example: Instruction X is an ECNT instruction, which just detected an edge). The malfunction does NOT occur if the data field of instruction X does not change, since then b) is not true.
Vendor:ZETEXPackage Cooled:ZETEXD/C:04+
2. Instruction X just changes its data field (in time slot Y). (Example: Instruction X is an ECNT instruction, which just detected an edge). The malfunction does NOT occur if the data field of instruction X does not change, since then b) is not true.
Vendor:ZETEXPackage Cooled:50000
Clock • Built-in PLL clock frequency multiplication circuit • Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 4 times of oscillation clock (for 4-MHz oscillation clock, 4 MHz to 16 MHz). • Operation by sub-clock (8.192 kHz) is allowed. (MB90F897) • Minimum execution time of instruction: ...
Vendor:ZETEXPackage Cooled:MSOP-8D/C:00+
Small Size Industry Standard Footprint Compatible with IR Solder Diffused Optics Operating Temperature Range of -30C to +85C • Right Angle Package Available • Five Colors Available • Available in 8 mm Tape on 7 in. (178 mm) Diameter Reels
Vendor:ZETEXPackage Cooled:MSOP-8D/C:00+
Small Size Industry Standard Footprint Compatible with IR Solder Diffused Optics Operating Temperature Range of -30C to +85C • Right Angle Package Available • Five Colors Available • Available in 8 mm Tape on 7 in. (178 mm) Diameter Reels
Vendor:ZETEXPackage Cooled:ZETEXD/C:04+
Note 10: This output data pulse position works for TTL inputs except the LVDS output bit mapping difference (see Figure 8). Figure 9 shows the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
Vendor:MSOP8Package Cooled:ZETEXD/C:2004
Note 10: This output data pulse position works for TTL inputs except the LVDS output bit mapping difference (see Figure 8). Figure 9 shows the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
Vendor:ZETEXD/C:01+
While Atmel provides four options for implementing a gate array design, they all have the same basic flow. Data base acceptance is the first milestone. This is when Atmel receives and accepts the complete design data base. Preliminary design review is where the performance of the design is set based on the Cadence simulation. Final design review is the last review of the design before making masks. Th...
Package Cooled:SO-8
5V power supply 5V power supply 5V LNA power supply RF input LNA ground Ground Access to VCO control voltage VCO ground Ground Reference oscillator crystal Reference oscillator crystal IF AGC capacitor for OOK Reference for FSK Demodulated data (OOK & FSK modulation) State Machine Reset SPI interface I/O SPI interface I/O SPI interface clock 5V digital power supply Digital ground ...
‡ Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input vol...
Vendor:ZETEXPackage Cooled:08+D/C:04+
Test Condition: 1.0KHz / 1V. Electrical specifications at 25C. Temperature Rise: 40C. Operating temperature: -20C TO +105C. Insulation Resistance: 100M OHMS at 500VDC. Rated Voltage: 100V to 270V / 50-60 Hz. Hi-Pot Voltage: 1500VAC for one minute.
Package Cooled:08+D/C:1500
Main CLK(Hz)Under 3.58M7.16M10.74M14.3M Operating Voltage(min)2.22.533.6 • 16k x 13 on chip Program Memory • 0.5k x 8 on chip data RAM • Up to 21 bi-directional tri-state I/O ports(4 shared with AD input; 1 shared with external interrupt input ) • 12 level stack for subroutine nesting • 8-bit real time clock/counter (TCC) • Two 8-bit counters : COUNTER1 and COUNTE...
Package Cooled:08+D/C:1500
Main CLK(Hz)Under 3.58M7.16M10.74M14.3M Operating Voltage(min)2.22.533.6 • 16k x 13 on chip Program Memory • 0.5k x 8 on chip data RAM • Up to 21 bi-directional tri-state I/O ports(4 shared with AD input; 1 shared with external interrupt input ) • 12 level stack for subroutine nesting • 8-bit real time clock/counter (TCC) • Two 8-bit counters : COUNTER1 and COUNTE...
Vendor:ZETEXPackage Cooled:SOP-8D/C:3
A loopback test mode is provided that puts the driver outputs to a high impedance tri-state level, and routes the driver outputs to their associated receiver inputs. In this configuration, the signal path is non-inverting from the TTL driver input to the receiver TTL output. This operating mode allows the controlling system to perform diagnostic self-test of the RS-232/ RS-422 driver/receiver circu...
Vendor:ZETEXPackage Cooled:SOP-8D/C:03+
CONVENTIONS Unless otherwise noted, a positive logic (active High) convention is assumed throughout this docu- ment, whereby the presence at a pin of a higher, more positive voltage (nominally 5VDC) causes assertion of the signal. A # symbol following the signal name, e.g., RESET#, indicates that the sig- nal is asserted in a Low state (nominally 0 volts).
Vendor:ZETEXPackage Cooled:SOP-8D/C:03+
CONVENTIONS Unless otherwise noted, a positive logic (active High) convention is assumed throughout this docu- ment, whereby the presence at a pin of a higher, more positive voltage (nominally 5VDC) causes assertion of the signal. A # symbol following the signal name, e.g., RESET#, indicates that the sig- nal is asserted in a Low state (nominally 0 volts).
Vendor:ZETEXPackage Cooled:MSOP-8?D/C:08+
a watchdog timer (except for STM704/795/806) as well as a power-fail comparator (except for STM795) to provide the system with an early warning of impending power failure. These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package.
Vendor:ZETEXPackage Cooled:SOP8D/C:06+
a watchdog timer (except for STM704/795/806) as well as a power-fail comparator (except for STM795) to provide the system with an early warning of impending power failure. These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package.
Package Cooled:SMD-8D/C:800
RDY/BUSY: An open drain READY/BUSY output pin pro- vides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open drain connection a llo ws fo r OR-tying o f seve ral de vices to th e same RDY/BUSY line.
Package Cooled:08+D/C:800
RDY/BUSY: An open drain READY/BUSY output pin pro- vides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open drain connection a llo ws fo r OR-tying o f seve ral de vices to th e same RDY/BUSY line.
D/C:08+/09+
10,000 cycles/byte, minimum 1,000 cycles/byte, minimum 100,000 cycles/byte, minimum -2.0 V dc to +7.0 V dc -65C to +150C 1.0 W +300C +150C See MIL-STD-1835 13C/W 27C/W -2.0 V dc to +7.0 V dc -2.0 V dc to +13.5 V dc -2.0 V dc to +14.0 V dc -2.0 V dc to +7.0 V dc 200 mA 10 years minimum
Vendor:ZETEXPackage Cooled:SMD-8D/C:04+
When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All outputs become high impedance, and all inputs are treated as dont care. If a valid access is in process at the time of power-fail detection, the memory cycle continues to com- pletion. If the memory cycle fails to terminate within time tWPT, write-protection takes place.
Package Cooled:SMD-8D/C:800
When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All outputs become high impedance, and all inputs are treated as dont care. If a valid access is in process at the time of power-fail detection, the memory cycle continues to com- pletion. If the memory cycle fails to terminate within time tWPT, write-protection takes place.
Vendor:ZETEXPackage Cooled:MLP832D/C:6
Vendor:ZETEXPackage Cooled:MLP832D/C:6
Vendor:ZETEXPackage Cooled:3X2 MLP-8D/C:07+
MultiMediaCard (MMC) Form Factor Single 2.7V to 3.6V Supply 20 MHz Max Clock Frequency Serial Peripheral Interface (SPI) Compatible Low Power Dissipation C 4 mA Active Read Current Typical C 2 µA CMOS Standby Current Typical • Industrial Temperature Range
Vendor:ZETEXPackage Cooled:SMD-8D/C:04+
Vendor:ZETEXPackage Cooled:SMD-8D/C:04+
This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle.
Vendor:-Package Cooled:★Original and new, Special price!D/C:05+06+
The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The ZXMC4559DN8TA/48 have noninverting inputs; the ZXMC4559DN8TA/49 have inverting inputs. On the ZXMC4559DN8TA and ZXMC4559DN8TA, a high on IN results in a high on HIGHDR. On the ZXMC4559DN8TA and ZXMC4559DN8TA, a high on IN results in a low on HIGHDR.
Vendor:ZETEXPackage Cooled:MSOP-8D/C:03
Todo el material que no es necesario fu retirado del embalaje del producto. Intentamos, en cada proyecto, hacer embalajes cuyas partes sean de facil separacin y tambin materiales reciclables, como almohadillas de poliestireno, cartn corrugado y bolsas de plstico. Intente hacer el descar te del embalaje de manera conciente, y de preferencia destinndolo para recicladores.
Vendor:ZETEXPackage Cooled:MSOP-8D/C:06+
Todo el material que no es necesario fu retirado del embalaje del producto. Intentamos, en cada proyecto, hacer embalajes cuyas partes sean de facil separacin y tambin materiales reciclables, como almohadillas de poliestireno, cartn corrugado y bolsas de plstico. Intente hacer el descar te del embalaje de manera conciente, y de preferencia destinndolo para recicladores.
Vendor:ZETEXPackage Cooled:MSOP-8D/C:06+
MXIC's Automatic Programming algorithm requires the user to only write a program set-up command and a program command (program data and address). The device automatically times the programming pulse width, provides the program verify, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to t...
Vendor:ZETEXPackage Cooled:MSOP-8D/C:06+
MXIC's Automatic Programming algorithm requires the user to only write a program set-up command and a program command (program data and address). The device automatically times the programming pulse width, provides the program verify, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to t...
Vendor:ZETEXPackage Cooled:MSOP-8D/C:06+
This output pin is normally at a low level, but is momentarily driven high at the beginning of every timing period. The duration of the pulse is fixed at 60 cycles of the clock input (nominally 1 second with a 60Hz input). This output will not assume a high level following a circuit reset until there has been a valid clock transition.
Vendor:ZETEXPackage Cooled:MSOP-8D/C:06+
UV (Pin 3): Analog Undervoltage Input. When UV is pulled below the 1.125V threshold, an undervoltage condition is detected and the GATE pin will be immedi- ately pulled low. The GATE pin will remain low until UV rises above the 1.255 threshold.
Vendor:ZETEXPackage Cooled:MSOP-8D/C:06+
UV (Pin 3): Analog Undervoltage Input. When UV is pulled below the 1.125V threshold, an undervoltage condition is detected and the GATE pin will be immedi- ately pulled low. The GATE pin will remain low until UV rises above the 1.255 threshold.
Vendor:ZETEXPackage Cooled:TSSOP8D/C:99/00+
The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques.
8. CPD, measured per function, is used to determine the dynamic power consumption. PD (per package) = VCC ICC + (VCC2 fl CPD + VO2 fO CL + VCC ∆lCC D) where: VCC = supply voltage ∆lCC = flow through current x unit load CL = output load capacitance D = duty cycle of input high fO = output frequency fI= input frequency